|Project No.||Project Name||Responsible|
Metallization Systems for Nanoelectronics
|Prof. Dr. Thomas GESSNER
Prof. Dr. Stefan E. SCHULZ
The metallization of integrated circuits for high performance applications involves application of copper damascene interconnects together with low-k dielectrics. Both approaches of low resistivity interconnects and low capacitance dielectrics are capable of providing low para-sitics and therefore reduced RC delay and cross talk. Copper is additionally able to carry higher currents and to offer better reliability compared to aluminum. Copper/low-k intercon-nects currently in production involve PVD of barrier and seed layers followed by the electro-chemical deposition (ECD) of copper as well as dense CVD low-k dielectrics (SiCOH materi-als). Further scaling of interconnects to nanoscale dimensions and maintaining the envisaged RC delays and reliability below the 65 nm technology nodes require new materials and depo-sition techniques [G1-1] or completely new approaches (e.g. air gap architectures). The fol-lowing key challenges have to be resolved in the future and solutions developed for an appli-cation in integrated circuits in a perspective of 5-10 years from now and more:
In the framework of the IRTG the interconnect group at the ZfM/TU Chemnitz will concentrate on the following subjects:
New Cu CVD precursors developed by Prof. Lang's group (G5) will be evaluated for their potential to be applied in Cu damascene interconnect formation as seed layers or complete via/trench fill in nanoscale features. Besides establishing precursor delivery and appropriate CVD processes, critical issues to be considered are interfacial adhesion, microstructure, resis-tivity, and filling behavior. Characterization will be done in co-operation with G8 and F7. Advanced surface enhancing techniques can be used to provide good filling capabilities. Dif-ferent options will be considered like supercritical fluid deposition (SFD), self-assembled monolayers (SAMs; co-operation with F6) and catalyst addition. Research on Cu ALD for providing conformal ultrathin seed layers will be an option. The ALD route will be to deposit a Cu oxide film either on atomic layer scale with in situ reduction to pure Cu or to deposit Cu oxide by ALD and perform an final ex situ reduction step to a pure Cu film.
To improve the interface on top of Cu damascene interconnects to the adjacent dielectric (di-electric barrier/interlevel dielectric) different approaches will be evaluated. Cu surface treat-ments, e.g. with SiH4/NH3 leading to the formation of CuSiN, were investigated to diminish the Cu migration path at this weak interface and thus improving electromigration stability [G1-2]. A second approach is the selective deposition of a conducting barrier material, for which electroless CoWP or NiMoP are currently under investigation [G1-3]. Overgrowth currently limits a potential application because of the risk of shorts or increased leak-age/lower breakdown strength. We intend to investigate the potential of CVD/ALD tech-niques to selectively form ultra thin barrier films on top of Cu lines. Former works showed that this is possible, e.g. for W CVD. The goal will be a controlled selective growth of a few nanometers without degradation of the interconnect properties. The different surfaces (insula-tors, Cu) have to be investigated with respect to their potential to adsorb or not adsorb the precursors to provide a selective growth. Special wet or plasma chemical treatments will be developed to enhance the growth selectivity. To finally assess the impact on the interconnect reliability at nano-interconnects a co-operation is planned with the reliability group at the University Hanover.
The investigation of low-k dielectrics focuses on porous materials with an ultra or extreme low k-value (k < 2.1) envisaged for first application in about 5-8 years. Characterization of porous ULK film properties will be performed by investigating electrical (k, leakage, break-down), mechanical (internal stress, CTE, adhesion; Young's modulus and yield strength in G6), thermal (thermal conductivity) properties and pore characteristics (pore size and its dis-tribution, porosity in cooperation with G7). Especially the electrical characterization of highly porous materials suffers from insufficient understanding of the interactions of meas-urement probe (Hg probe, Al electrodes) with the porous material and therefore occurring measurement errors and inconsistencies. Furthermore, charge transport and conducting mechanisms which are important for leakage and breakdown interpretation are not well un-derstood for those porous dielectrics. Therefore, the goal is to perform basic investigations to improve the understanding of these important mechanisms.
An alternative or successor to the challenging integration of porous ULK dielectric materials for achieving lower capacitive coupling is the introduction of air cavities with k~1 between narrow lines, especially in the lower metal levels. Different concepts were examined up to now, which basically allow a level by level air gap formation. They often rely on sacrificial polymers, which are decomposed or selectively etched after metal level formation. But this bears the same risk for integration, as already experienced with C-polymer-based low-k ma-terials, like mechanical weakness and CTE mismatch. On the other hand so-called close-off approaches use additional patterning and etching of cavities in between already formed Cu damascene lines and following closure at the top by using a selective dielectric CVD process. Our approach will use conventional dense materials like SiO2 or SiCOH which are etched through self aligned slots with below lithography dimensions of about 10 nm width after em-bedded Cu interconnect formation. These slots can be achieved e.g. by sidewall modification of the dielectric (e.g. for SiCOH) or by using ultrathin spacer materials before barrier/metal deposition in the trenches. The self-aligned slots provide the advantage of easy closure by CVD techniques because of the very small dimensions. First tests have been performed at ZfM, which show that such an approach is feasible. Concepts of mechanical stabilization as well as for multilevel approaches have to be developed. The goal will be to allow self-aligned air gap formation with a minimum number of process steps added. Finally, the air gap con-taining metallization will be assessed with respect to electrical properties like metal line re-sistance, interline capacitance, leakage and breakdown including FEM simulations to allow extraction of the effective k-value.
The investigation of new interconnect approaches for global interconnects like optical and wireless on-chip interconnects will be an important option, which will be followed by taking into account the international trends and the respective capabilities at the ZfM.
Co-operation is especially planned with G6 (mechanical characterization), G7 (optical characterization, G8 (structural and morphological characterization), F2 (low-k dielectrics and Copper interconnects) and F3 (diffusion barriers, integration with low-k).
|[G1-1]||ITRS Roadmap, Sematech & SIA, 2003 and 2004 update.|
|[G1-2]||S. Chhun et al., Microelectronic Engineering 76 (2004) no.1-4, p.106-12.|
|[G1-3]||For example: T. Ishigami et al., in: Proc. IITC 2004, IEEE, Piscataway (ISBN 0-7803-8309-5).|