|Project No.||Project Name||Responsible|
Advanced processes, materials and their integration into nanoelectronics interconnect systems
|Prof. Dr. Stefan E. SCHULZ
Dr. Knut SCHULZE
Interconnects are still considered to be one of the major challenges in future nanoelectronics technologies according to the ITRS [G1-1]. Within subproject G1 we will address research contributions to fulfill future nanoelectronic device requirements as well as alternative, partly disruptive processing technologies. To adress further scaling issues in technology nodes below 28 nm, we plan to perform research on:
Ultrathin film materials are one of the current and near-term issues of the ITRS. Based on the research work of the first IRTG period, the developed ALD processes will be used to provide highly conformal ultrathin Cu seed layers. Beside the main focus of highly conformal deposition also in aspect ratios of 4 to 5 and minimum line width of 15 up to 20 nm (ITRS protection for 2020), these materials must provide improved growth behavior and adhesion strength on ultrathin diffusion barriers. Finally, sufficient conductivity is required to ensure reliable electrochemical deposition processes (ECD) for via or trench fill using ultrathin seed layers. Furthermore, new ALD precursors developed by Prof. Lang’s group (G5) will be evaluated for the specified applications. Characterization will be done in co-operation with G7 and G8.
Since conventional scaling of interconnect systems faced the limits in the past years, 3D silicon integration is a proposed solution that promises to simultaneously increase chip-level performance and decrease overall power consumption while boosting transistor density and computational power per unit volume [G1-2]. Preparation (dry etch with respective shape), isolation and filling (CVD or ECD) of high density through-silicon-vias (TSV) as inter-chip interconnects with aspect ratios of >10 are major topics in G1 for providing appropriate processes to be integrated in 3D integration process flows.
Striving for the integration of porous materials to reduce the RC delay in interconnect systems and nanoscale diffusion barriers, a multitude of integration issues and material interactions appear. Investigations will be performed to improve the basic understanding of the interface of porous materials and conductive diffusion barriers. Moreover, damage of porous low-k materials by etching, stripping or cleaning processes related to interface formation will be part of the research work. Additionally, surface activation of patterned porous low-k materials for ALD of diffusion barriers is a promising approach for the fabrication of advanced nanoscale interconnects. The formation of reliable interfaces of porous low-k materials and nanoscale diffusion barriers will be the focus - including poresealing techniques, e. g. application of liners or plasma surface densification.
Carbon nanotubes are a potential candidate as interconnect material in advanced nanostructures. The application of the CNT-technology and experience obtained in the first IRTG phase to realize CNT-based via architectures and characterization of them are the main focus. Several challenges are planned to be addressed: such as low-temperature growth, high conductivity of the CNTs, as well as the metal/CNT interface, process design, reproducibility, and reliability. For low-temperature growth on the one recent processes are going to be optimized, on the other hand several catalyst systems including binary materials will be applied and evaluated. To achieve highly conductive interconnects several metallization/catalyst systems will be investigated Moreover, different CNT top contacting processes will be investigated and optimized to achieve a good metal-CNT contact.
Characterization will focus on electrical as well as thermal evaluation beside structural analysis of the via structures (collaboration with G2). Reproducibility as an important integration issue will be targeted by further improvement of processes and equipment.
An alternative to or successor of the challenging integration of porous ULK dielectric materials for achieving lower capacitive coupling between interconnect lines is the introduction of air cavities with k~1 (“airgaps”) between narrow lines, especially in the lower metal levels. Different airgap concepts developed at the ZfM following the sacrificial layer approach using SiO2 show the feasibility of this technology at relaxed feature sizes [G1-3]. The application of the well approved material system SiO2 / Cu offers a reasonable manufacturing of such architectures. Consequently, these technologies will be implemented using pattern geometries less than 800 nm. Therefore, preparation and characterization of such architectures will be performed.
|[G1-1]||ITRS Roadmap, Sematech & SIA, 2007 and 2008 update.|
|[G1-2]||S. Chamma et al., Integrated circuits 3D silicon integration (2009), Proceedings of the 4th International Conference on Systems, ICONS 2009, art. no. 4976344, pp. 204-209||[G1-3]||K. Schulze et al., Airgap Structures by using Sacrificial Wet Etch: Fabrication, Thermal and Mechanical Behavior, Reliability, Advanced Metallization Conference (AMC), San Diego, CA (USA), 2008 Sep 23-25; MRS Conf. Proc. AMC XXIV, Materials Research Society, Warrendale PA (2007), pp 41-52 (ISBN 1-60511-125-4 / ISSN 1048-0854)|