First project period 04/2006 - 09/2010

Project No. Project Name Responsible
G4 Development of an elastic under bump structure for wafer level packaging Prof. Dr. Herbert REICHL
Oswin EHRMANN

Description

The International Technology Roadmap for Semiconductors (ITRS) views wafer level packaging (WLP) as a promising solution for future packaging and interconnect challenges. The WLP process is a technology in which all steps of integrated circuit packaging are performed at the wafer level. Unfortunately, there are a few issues in WLP.

Conventional WLP technologies use rigid gold or solder bumps as interconnect elements. The CTE mismatch between the silicon of the chip and the organic material of a printed wiring board causes thermo-mechanical stress in the interconnects. The thermally induced cycles during the operation time of the IC cause a restricted reliability especially for large chips. Today this issue is solved by the application of an underfiller material in the gap between chip and substrate.

However, the usage of underfiller has the disadvantage that exchange and repair of a bonded die is not possible. Rigid bumps are also an unfriendly contact system for test and burn-in on wafer level. The development of an elastic interconnect structure will overcome these issues.

In the proposed development work electroplated metal structures will be evaluated to build such elastic elements. One promising option is a metallization in spiral shape that forms spring type structures. Such a structure has to be plated on a separation layer which can be removed. After stripping, the mechanical element becomes movable.

Workpackages

  1. Evaluation of metals to be used for plating of the elastic structures
  2. Evaluation of materials for the separation layer (e.g. metals, polymers) with the following requirements:
  3. Design optimization under mechanical view
  4. Processing of test wafers
  5. Assembly of test vehicles
  6. Reliability testing

The development work will be implemented at the Fraunhofer Institute for Reliability and Micro Integration (IZM) in Berlin and Berlin Technical University in cooperation with the institute of Prof. Gessner at Chemnitz University of Technology. The requested photo resist processes will be developed in cooperation with the subproject SJ1 (Prof. Di Chen, Shanghai Jiao Tong University). Material data for the simulation of the microstructures will be measured in subproject G6 (Prof. F. Richter, TU Chemnitz). Microscopic imaging of critical struc-tures, interfaces, and defective features will be performed in cooperation with subproject G8 (Prof. Hietschold, TU Chemnitz).