3-D integration is the most promising research topic currently in the area of Advanced Packaging. Most of these new technologies are based on through-silicon vias (TSV). The major issue of TSV is the nature of the Si material. It is neither a conductor nor is it an isolator. Therefore if Si is acting as an interposer or a carrier for an IC it has to be isolated by a barrier-type material and filled by a highly conductive material like Cu or Ti. The focus of this proposal is on a new type of polymeric isolation and conductive material previously used in the PWB industry (solder pastes). This new polymeric materials is based on parylene which is deposited by vapor deposition. The dimmer is melted at very high temperature (above 500°C) which breaks the bonds between the two monomers. These highly reactive monomers can polymerize at room temperature on any geometrical structure. The deposition is therefore perfectly conformal. These kinds of conformal coatings are necessary for TSV because the Si holes are drilled by reactive ion etching (nearly straight side walls). The highspeed deposition is a big benefit compared to CVD methods based on inorganic materials. The surface quality is perfectly shaped for printing conductive pastes inside the vias. There is no need of high costly sputtering and plating of Cu. Up to now isolation and Si via-filling is the major hurdle for the transfer of 3D integration to production due to immense processing costs. The combination of parylene coating and solder paste filling is highly promising approach for high volume manufacturing [G4-1]-[G4-4]. The goal of this proposal is the investigation of the basic parameters for the process technology. The electrical and reliability performance of the built-up structure will be evaluated. A major focus will be the understanding between the interfaces of the polymer layer to the Si via and the solder filled hole.
| [G4-1] |
M. Töpper, The Importance of Polymers in WLP, Materials for Information Technology (E. Zschech, C. Whelan, T. Mikolajick, Ed.), Springer Verlag, 2005, pp. 347 - 362, ISBN-10: 1-85233-941-1 |
| [G4-2] |
M. Töpper, D. Tönnies, Microelectronic Packaging (Chapter 21), Semiconductor Manufacturing Handbook (M.h. Geng, Ed.), McGraw-Hill, 2005, ISBN: 0-07-144559-5 |
| [G4-3] |
M. Töpper, Wafer Level Chip Size Packaging, Materials for Advanced Packaging (Hrsg.: D. Lu, C.P. Wong), Springer Verlag 2009, pp 547 – 600, ISBN: 978-0-387-78218-8 |
| [G4-4] |
H. Reichl, R. Aschenbrenner, M. Töpper, H. Pötter, Heterogeneous Integration - Building the Foundation for Innovative Products, More than Moore (Hrsg. G. Q. Zhang, A.j. van Roosmalen), Springer Verlag, pp 279 – 303, ISBN 978-0-387-75592-2 |